It is well known that the capacitance value of a ceramic capacitor varies as a function of the area of facing surfaces of capacitor electrodes and the spacing therebetween, as well as other factors such as dielectric constants. The capacitance may be increased by decreasing the spacing between electrodes. However, in the case of ceramic capacitors a problem is presented in the handling of sheets or strips of ceramic greenware when the thickness decreases below 0.001 inch. Thin sheets of ceramic greenware when fired quickly distort at the edges. Stripping of thin ceramic green ware film from the base on which the film is cast is a difficult and delicate operation as there is a tendency for the thin greenware film to tear and to fold over upon itself. Today, let’s introduce a new and improved method of making ceramic capacitors utilizing very thin ceramic dielectric, and provides a capacitor of increased capacitance value through thinner dielectric separation.

Briefly stated, the invention in one form thereof, comprises the steps of defining a first pattern of electrodes on a release surface, casting a very thin layer of a ceramic on said release surface over said patterns, applying a second pattern of electrodes on the top or other side of the thin film of ceramic, then positioning a thicker layer of green ceramic on top of the cast film, applying sufficient pressure to at least partially consolidate the surfaces of the strips of ceramic, and removing both strips of ceramic from the release surface. If a single layer capacitor is desired, then a second cover strip is applied over the exposed electrode pattern. If multi-layer capacitors are desired, the assembly of the very thin strip and the backing strip may be stacked to the desired thickness. Thereafter, the assembly may be pressure laminated. Individual capacitors are then cut from the assembly, or one surface may be scored along the edges of the electrodes to permit later separation of capacitors from a multiple fired assembly.

The chip capacitor researched and developed by EXSENSE Electronics Technology Co., Ltd. has the characteristic of large capacitance, small size, good solderability, it is convenient for customers to match the capacitance width with the conductor line width of the circuit board, or to accommodate the capacitance size when the circuit area is limited, or to customize different sizes and parameters according to customer requirements.

Reference Data:

Inventor: Gilbert J. Elderbaum, 896 Main St.,

Lynnfield Center, Mass. 01940

Filed: May 5, 1975

Appl. No.: 574,589

Related U.S. Application Data

Continuation-in-part of Ser. No. 359,229, May 1 1,

1973, Pat. No. 3,882,059.

U.S. C. ............................... 29125.42; 3611272

Int. Cl....................... H01G 4/12; H01G 4/30

Field of Search .............. 29/25.42; 264/61, 67;

317/261

References Cited

UNITED STATES PATENTS

2,53,389 1 1/1950 Brandt .............................. 29/25.42

3,021,589 2/1962 Weller .............

3,235,939 2/1966 Rodriquez .......

- - - - - - 29/25.42

- - - - - - - - - - - - - 29/25.42

3,236,707 2/1966 Lins ........................... 29125.42 UX

3,466,513 9/1969 Belko, Jr. et al.................. 3171261

Primary Examiner-Carl E. Hall